The invention relates to a method for producing an integrated ferroelectric or DRAM semiconductor memory configuration on a wafer substrate, as disclosed, for example, in Japanese Patent document JP 05243521 A together with the associated abstract.
The magnitude of the polarization that can be changed over or the charge that can be stored on the capacitor plates is of crucial importance for the functionality and also the reliability of ferroelectric memories (FeRAMs) and DRAMs with a high dielectric constant xcex5. The voltage on the bit line (BL) that is caused by the polarization or charge during reading must not fall below a minimum value specified for the product. In the simplest case, the BL signal can be increased by enlarging the capacitor area, but this is accompanied by an increase in the chip area.
Attempts have already been made to increase the BL signal by reducing the thickness and also by construction optimizations (low bit line capacitance) and also by a suitable choice of the ferroelectric or dielectric (high dielectric constant xcex5). However, technological limits are imposed on these routes because these measures usually entail enlargement of the capacitor area to the detriment of the packing density.
In known memory cells, usually, only one storage capacitor is addressed per selection transistor. Consequently, it is also the case that only one bit of information can be stored for each address.
The abovementioned Japanese Patent document 05243521 A (abstract) shows a DRAM memory cell in which, in order to increase the storage capacitance of the storage capacitor while maintaining a minimum chip occupation area, two storage capacitors with first and second electrodes that are interleaved in one another in a comb-like manner are formed in an insulating substrate layer such that they are symmetrical with regard to a source electrode and a drain electrode of the selection transistor. In accordance with FIG. 1 of this Japanese Patent document, respective electrodes of these storage capacitors lying one above the other are jointly electrically connected to the drain region of the selection transistor.
German Published, Non-Prosecuted Patent Application DE 38 40 559 A1, corresponding to U.S. Pat. Nos. 4,978,635 and 4,959,709 to Watanabe, describes a semiconductor memory device and a production method provided therefor, in which a storage capacitance element connected to a source or drain electrode of a selection transistor embodied as a MOSFET is formed from the rear side of a silicon substrate. The storage capacitance element is formed as a trench capacitor in a trench produced from the rear side of the silicon substrate.
U.S. Pat. No. 5,684,316 to Lee describes a semiconductor memory device with two storage capacitors formed above and below a cell transistor. The method described therein that is used to form the storage capacitors proceeds such that firstly a first storage capacitor is formed on the topside of a first substrate. The structure of the first storage capacitor is, then, connected to a second substrate, and the resulting structure is rotated such that the previous top side faces downward. Afterward, the cell transistor structure including two transistors is constructed and, finally, a second storage capacitor is produced thereabove.
It is accordingly an object of the invention to provide a method for producing an integrated semiconductor memory configuration, in particular, for a DRAM or a ferroelectric semiconductor memory configuration, that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that makes possible a higher packing density of the memory cells or achieves a significantly higher read signal for the same cell area.
With the foregoing and other objects in view, there is provided, in accordance with the invention, an integrated ferroelectric or DRAM semiconductor memory configuration produced on a wafer substrate, a selection transistor and two storage capacitors that can be addressed by the selection transistor being formed per memory cell, and forming the two storage capacitors for each memory cell respectively from the front and rear sides of the substrate.
The method is characterized by the following steps:
A) preparation of a substrate wafer and formation of electrode regions of the selection transistor as CMOS transistor from the front side of the wafer;
B) etching a recessed region in the rear side of the wafer;
C) formation of a first electrically conductive plug within the recessed region so that the first plug makes contact with an electrode region of the selection transistor formed in the step (A);
D) formation of a first storage capacitor in the recessed region from the rear side of the wafer so that an electrode plate of the first storage capacitor, which electrode plate faces the electrode region of the selection transistor, is electrically conductively connected to the electrode region of the selection transistor by the plug formed in the step (C);
E) formation of a second electrically conductive plug from the front side of the wafer so that the second plug comes into contact with the same electrode region of the selection transistor; and
F) formation of a second storage capacitor from the front side of the wafer so that an electrode plate of the second storage capacitor, which electrode plate faces the electrode region of the selection transistor, comes into contact with the electrode region of the selection transistor by the second plug formed in step (E).
In a particular configuration, it is desirable to be able to store more states than only either 0 or 1 per memory cell, i.e., per address.
In one procedure, steps (A) to (F) may be performed in the above-indicated order. An alternative method procedure combines steps (A), (E), and (F) and performs them before the subsequent steps (B), (C), and (D).
Yet another alternative method forms the storage capacitors on the two wafer sides in parallel, i.e., approximately simultaneously, and performs as many etchings, depositions, maskings, etc. as possible on the two wafer sides.
By incorporating the rear side of the wafer, it is possible to achieve a more effective utilization of the chip area of an integrated semiconductor memory configuration produced in this way. The proposed process forms two storage capacitors that can be addressed by the same selection transistor and require the same chip area as previously required by just one storage capacitor. The capacitance-forming area of the associated storage capacitors and, thus, the stored charge or polarization, thus, increase by two-fold for the same chip area. This can be utilized either in the form of an increased reliability (higher bit line signal) or in a further reduction of the chip area.
In accordance with another mode of the invention, there is provided the step of introducing a first insulating layer in the recessed region from the rear side of the wafer and covering the first storage capacitor to electrically insulate the first storage capacitor with the first insulating layer and protect the first storage capacitor from damage by subsequent processing steps.
In accordance with a further mode of the invention, there is provided the step of applying a second insulating layer to the front side of the wafer and covering the storage capacitor to electrically insulate the second storage capacitor with the second insulating layer and protect the second storage capacitor from damage by subsequent processing steps.
If, in a ferroelectric memory configuration in accordance with one proposal of the present invention, the ferroelectric films of the two storage capacitors are formed with different thicknesses and/or the areas of the two storage capacitors are formed with different sizes and/or the chemical compositions of the ferroelectrics of the two storage capacitors are formed differently, such a procedure makes it possible to store two bits per address, i.e., per selection transistor. By way of example, if the ferroelectric films in the two storage capacitors are deposited with different thicknesses, the coercive voltages (i.e., the voltage at which the polarization starts to switch) have different values. Depending on the magnitude of the read-out voltage, it is possible to address only one or both storage capacitors. By a corresponding evaluation circuit, it is, then, possible to differentiate four states (00, 01, 10, 11) at one address. In addition to the different thickness of the ferroelectrics, it is possible, as mentioned, to differentiate the two storage capacitors also in terms of their area or in terms of their material and, thus, in terms of the stored charge/polarization. The voltage levels during reading, then, permit conclusions in respect of which or whether both storage capacitors were at a high level or low level.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for producing an integrated semiconductor memory configuration, it is, nevertheless, not intended to be limited to the details shown because various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof, will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.